
#pragma	ident	"@(#)dma_reg.h 1.2	94/06/22 SMI"

/*
 * Copyright (c) 1992, Sun Microsystems, Inc.  All Rights Reserved.
 * Sun considers its source code as an unpublished, proprietary
 * trade secret, and it is available only under strict license
 * provisions.  This copyright notice is placed here only to protect
 * Sun in the event the source is deemed a published work.
 * Disassembly, decompilation, or other means of reducing the
 * object code to human readable form is prohibited by the license
 * agreement under which this code is provided to the user or
 * company in possession of this copy.
 *
 * RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the
 * Government is subject to restrictions as set forth in
 * subparagraph (c)(1)(ii) of the Rights in Technical Data and
 * Computer Software clause at DFARS 52.227-7013 and in similar
 * clauses in the FAR and NASA FAR Supplement.
 *
 * These examples are provided with no warranties of any kind,
 * including without limitation accuracy and usefulness, and Sun
 * expressly disclaims all implied warranties of merchantability,
 * fitness for a particular purpose and non-infringement. In no
 * event shall Sun be liable for any damages, including without
 * limitation, direct, special, indirect, or consequential damages
 * arising out of, or relating to, use of these examples by customer
 * or any third party. Sun is under no obligation to provide support
 * to customer for this software.
 */


#define	DMA_NAME	"SUNW,dma"	/* name string in FCode prom */
#define	DMA_NREG	3

typedef struct dma {				/* per-unit structure */
	dev_info_t		*dip;
	kmutex_t		mutex;
	kcondvar_t		cv;
	ddi_iblock_cookie_t	iblock_cookie;	/* for mutexes */
	ddi_dma_handle_t	handle;
	struct buf		*bp;
	u_int			attach_flags;
	u_int			flags;
	Dma_csr			*csr;		/* mapped to CSR on device */
	Dma_addr		*addr;		/* data register on device */
	Dma_count		*count;
} Dma;

/*
 * default values for the limit structure
 */
#define	DMA_DEFAULT_LOWER	(u_long)0x00000000	/* any address */
#define	DMA_DEFAULT_UPPER	(u_long)0xFFFFFFFF	/* any address */
#define	DMA_DEFAULT_COUNTER	 (u_int)0xFFFF		/* 16-bit counter */
#define	DMA_DEFAULT_BURSTSIZE	 (u_int)0x0000007F	/* 1,2,4,8,16,32,64 */
#define	DMA_DEFAULT_MIN_XFER	 (u_int)1
#define	DMA_DEFAULT_SPEED	 (u_int)0		/* don`t care */

/*
 * bit fields for Dma.flags
 */
#define	DMA_DEV_OPEN	0x00000001
#define	DMA_DEV_BUSY	0x00000002

/*
 * bit fields for Dma.attach_flags
 */
#define	SOFT_STATE_ALLOCATED	0x01
#define	INTERRUPT_ADDED		0x02
#define	MUTEX_ADDED		0x04
#define	CSR_MAPPED		0x08
#define	ADDR_MAPPED		0x10
#define	COUNT_MAPPED		0x20
#define	MINOR_NODE_CREATED	0x40

/*
 * maximum transfer size
 */
#define	DMA_MINPHYS	0x0000FFFF	/* 64 K */

/*
 * other stuff
 */
#ifndef	TRUE
#define	TRUE	1
#define	FALSE	0
#endif	TRUE

#ifndef	OK
#define	OK	0
#endif	OK
