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/*
 * This file is a product of Sun Microsystems, Inc. and is provided for
 * unrestricted use provided that this legend is included on all tape
 * media and as a part of the software program in whole or part.  Users
 * may copy or modify this file without charge, but are not authorized to
 * license or distribute it to anyone else except as part of a product
 * or program developed by the user.
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 * 
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 *
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 * THIS FILE IS PROVIDED AS IS WITH NO WARRANTIES OF ANY KIND INCLUDING THE
 * WARRANTIES OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE, OR ARISING FROM A COURSE OF DEALING, USAGE OR TRADE PRACTICE.
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 * 
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 *
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 * This file is provided with no support and without any obligation on the
 * part of Sun Microsystems, Inc. to assist in its use, correction,
 * modification or enhancement.
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 * 
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 *
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 * SUN MICROSYSTEMS, INC. SHALL HAVE NO LIABILITY WITH RESPECT TO THE
 * INFRINGEMENT OF COPYRIGHTS, TRADE SECRETS OR ANY PATENTS BY THIS FILE
 * OR ANY PART THEREOF.
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 * 
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 *
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 * In no event will Sun Microsystems, Inc. be liable for any lost revenue
 * or profits or other special, indirect and consequential damages, even
 * if Sun has been advised of the possibility of such damages.
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 * 
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 *
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 * Sun Microsystems, Inc.
 * 2550 Garcia Avenue
 * Mountain View, California  94043
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 * 
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 *
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 * @(#)dma_io.h 1.1 93/02/12 Copyright 1993 Sun Microsystems
 */

/*
 * commands for dma_ioctl
 */
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#define	DMA_GET_CSR		_IOR('b', 1, Dma_csr)
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#define	DMA_IOC			('d' << 8)
#define	DMA_GET_CSR		(DMA_IOC | 1)
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/*
 * register definitions
 */
typedef u_short Dma_csr;
typedef u_short Dma_addr;
typedef u_short Dma_count;

/*
 * bit definitions for CSR
 */
#define	DMA_DEV_ENABLE	0x01
#define	DMA_INTR_ENABLE	0x02
#define	DMA_INTR_CLEAR	0x04
#define	DMA_DMA_ENABLE	0x08
#define	DMA_ERROR	0x10
#define	DMA_RESERVED3	0x20
#define	DMA_RESERVED4	0x40
#define	DMA_DONE_INTR	0x80

/*
 * useful combinations of the above
 */
#define	DMA_RESET	0x00
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