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/* @(#)dma_io.h	1.7 copyright 92/09/11 Sun Microsystems, Inc." */
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#pragma	ident	"%Z%%M% %I%	%E% SMI"

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/*
 * Copyright (c) 1992, Sun Microsystems, Inc.  All Rights Reserved.
 * Sun considers its source code as an unpublished, proprietary
 * trade secret, and it is available only under strict license
 * provisions.  This copyright notice is placed here only to protect
 * Sun in the event the source is deemed a published work.
 * Disassembly, decompilation, or other means of reducing the
 * object code to human readable form is prohibited by the license
 * agreement under which this code is provided to the user or
 * company in possession of this copy.
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 * 
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 *
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 * RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the
 * Government is subject to restrictions as set forth in
 * subparagraph (c)(1)(ii) of the Rights in Technical Data and
 * Computer Software clause at DFARS 52.227-7013 and in similar
 * clauses in the FAR and NASA FAR Supplement.
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 * 
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 *
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 * These examples are provided with no warranties of any kind,
 * including without limitation accuracy and usefulness, and Sun
 * expressly disclaims all implied warranties of merchantability,
 * fitness for a particular purpose and non-infringement. In no
 * event shall Sun be liable for any damages, including without
 * limitation, direct, special, indirect, or consequential damages
 * arising out of, or relating to, use of these examples by customer
 * or any third party. Sun is under no obligation to provide support
 * to customer for this software.
 */


/*
 * commands for dma_ioctl
 */
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#define	DMA_GET_CSR		_IOR('b', 1, Dma_csr)
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#define	DMA_IOC			('d' << 8)
#define	DMA_GET_CSR		(DMA_IOC | 1)
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/*
 * register definitions
 */
typedef u_short Dma_csr;
typedef u_short Dma_addr;
typedef u_short Dma_count;

/*
 * bit definitions for CSR
 */
#define	DMA_DEV_ENABLE	0x01
#define	DMA_INTR_ENABLE	0x02
#define	DMA_INTR_CLEAR	0x04
#define	DMA_DMA_ENABLE	0x08
#define	DMA_ERROR	0x10
#define	DMA_RESERVED3	0x20
#define	DMA_RESERVED4	0x40
#define	DMA_DONE_INTR	0x80

/*
 * useful combinations of the above
 */
#define	DMA_RESET	0x00
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